My bachelor's thesis: a low-cost HFT prototype on FPGA

The idea

My bachelor's thesis, developed with Lucas P. Flores, explores a low-cost academic prototype for high-frequency trading ideas using an ARM processor and an FPGA. The title is Development of a Low-Cost High-Frequency Trading System using HLS on FPGA.

The project does not connect to an exchange, does not send orders, and does not implement risk controls. It is a prototype for studying latency and hardware acceleration with synthetic market data.

What it does

A generator sends synthetic FIX Adapted for Streaming messages over TCP. A C++ receiver decodes those messages and converts the fields into 256-bit frames. On the DE10-Nano FPGA, VHDL modules move events through circular queues, maintain an aggregated order book with eight levels per side, and run a decision rule.

Part of the decision logic was written in MATLAB and converted to VHDL with HDL Coder. The bridge, order book, and wrappers stayed manually written in VHDL.

What was measured

In one recorded campaign with one million events, the FPGA core showed a three-cycle latency: 60 ns at 50 MHz. The reference C++ core averaged 315 ns.

The memory-mapped input/output path had an average round-trip latency of 10.228 us, a 99th percentile of 10.310 us, and streaming throughput of 102,381 messages per second.

Why it matters to me

The interesting part is not financial trading itself. The interesting part is the boundary between software, hardware, measurement, and design constraints. The project forced decisions about data representation, queues, timing, generated HDL, handwritten VHDL, and how to validate that the hardware path is doing what the software model says it should do.